Recently, as an error correction code to realize high error correction performance in a feasible circuit scale, an LDPC (Low-Density Parity-Check) code attracts attentions. An LDPC code provides high error correction performance and can be implemented in a simple manner, and is therefore adopted for error correction coding schemes in the fast wireless LAN system of IEEE802.11n and a digital broadcast system.
An LDPC code is an error correction code defined by a low-density parity check matrix H. Further, an LDPC code is a block code having the same length as the number of columns N of check matrix H.
However, like Ethernet (trademark), most of today's communication systems have a feature of grouping and communicating transmission information on a per variable-length packet basis or on a per frame basis. If an LDPC code, which is a block code, is applied to such systems, for example, a problem arises as to how a fixed-length LDPC code block is applied to a variable-length Ethernet (trademark) frame. In IEEE802.11n, although padding process and puncturing process are applied to a transmission information sequence to adjust the transmission information sequence length and the LDPC code block length, it is not possible to prevent a change of the coding rate and a redundant sequence transmission by padding and puncturing.
As such an LDPC code of a block code (hereinafter referred to as “LDPC-BC” (Low-Density Parity-Check Block Code)), an LDPC-CC (Low-Density Parity-Check Convolutional Code), which can encode and decode an information sequence of an arbitrary length, is studied (e.g. see Non-Patent Document 1 and Non-Patent Document 2).
An LDPC-CC is a convolutional code defined by a low-density parity check matrix, and, for example, FIG. 1 shows a parity check matrix HT[0, n] of an LDPC-CC of coding rate R=1/2 (=b/c).
Here, elements h1(m)(t) and h2(m)(t) of HT[0, n] have “0” or “1.”
Also, all the other elements than h1(m)(t) and h2(m)(t) included in HT[0, n] have “0.” M represents the memory length in the LDPC-CC, and n represents the codeword length of the LDPC-CC. As shown in FIG. 1, an LDPC-CC check matrix has a feature of a parallelogram shape, in which “1's” are assigned only to the diagonal elements and their nearby elements of the matrix and “0's” are assigned to the lower left elements and upper right elements of the matrix.
Here, referring to an example of coding rate R=1/2 (=b/c), in the case of h1(0)(t)=1 and h2(0)(t)=1, LDPC-CC coding is performed by implementing the following equation according to check matrix HT[0, n].
                    (                  Equation          ⁢                                          ⁢          1                )                                                                                  v                          1              ,              n                                =                      u            n                          ⁢                                  ⁢                              v                          2              ,              n                                =                                                    ∑                                  i                  =                  0                                M                            ⁢                                                                    h                    1                                          (                      i                      )                                                        ⁡                                      (                    n                    )                                                  ⁢                                  u                                      n                    -                    i                                                                        +                                          ∑                                  i                  =                  1                                M                            ⁢                                                                    h                    2                                          (                      i                      )                                                        ⁡                                      (                    n                    )                                                  ⁢                                  v                                      2                    ,                                          n                      -                      i                                                                                                                              [        1        ]            
Here, un represents the transmission information sequence, and v1,n and v2,n represent the transmission codeword sequences.
FIG. 2 shows an example of an LDPC-CC encoder that implements equation 1.
As shown in FIG. 2, LDPC-CC encoder 10 is formed with shift registers 11-1 to 11-M and 14-1 to 14-M, weight multipliers 12-0 to 12-M and 13-0 to 13-M, weight control section 17, mod 2 adder 15 and bit counter 16.
Shift registers 11-1 to 11-M and shift registers 14-1 to 14-M hold v1,n-i and v2,n-i (i=0, . . . , M), respectively, transmit the held values to the right neighboring shift registers at the timing the next inputs are entered, and hold the values transmitted from the left neighboring shift registers.
Weight multipliers 12-0 to 12-M and 13-0 to 13-M switch the values of h1(m) and h2(m) between 0 and 1, according to control signals transmitted from weight control section 17.
Weight control section 17 transmits the values of h1(m) and h2(m) at the timing to weight multipliers 12-0 to 12-M and 13-0 to 13-M, based on the count number transmitted from bit counter 16 and a check matrix held in weight control section 17. By performing mod 2 addition process for the outputs of weight multipliers 12-0 to 12-M and 13-0 to 13-M, mod 2 adder 15 calculates v2,n-i. Bit counter 16 counts the number of bits of transmission information sequence un received as input.
By employing such a configuration, LDPC-CC encoder 10 can perform LDPC-CC coding according to a check matrix.
An LDPC-CC encoder has a feature that this encoder can be realized with a very simple circuit, compared to a circuit that performs multiplication with a generation matrix and an LDPC-BC encoder that performs calculations based on the backward (forward) substitution method. Also, an LDPC-CC encoder is the encoder for convolutional codes, so that it is not necessary to separate a transmission information sequence into blocks of a fixed length and encode the results, and it is possible to encode an information sequence of an arbitrary length.
By the way, it is possible to apply the sum-product algorithm to LDPC-CC decoding. Therefore, it is not necessary to use decoding algorithms for performing maximum likelihood sequence estimation such as the BCJR algorithm and the Viterbi algorithm, so that it is possible to finish decoding process with low process delay. Further, a pipeline-type decoding algorithm is proposed utilizing the form of a parallelogram-shaped check matrix in which “1's” are assigned (e.g. see Non-Patent Document 1).
It is shown that, if LDPC-CC decoding performance and LDPC-BC decoding performance are compared using parameters by which the circuit scales of decoders are equal, LDPC-CC decoding performance is superior.
By the way, there is a demand to reduce the calculation scale by decreasing the number of iterations of iterative decoding in sum-product decoding. Up till now, as a technique for making the number of iterations smaller than in sum-product decoding, the shuffled BP (Belief-Propagation) decoding disclosed in Non-Patent Document 3 and the layered BP decoding disclosed in Non-Patent Document 4 are proposed.    Non-Patent Document 1: A. J. Felstorom, and K. Sh. Zigangirov, “Time-Varying Periodic Convolutional Codes With Low-Density Parity-Check Matrix,” IEEE Transactions on Information Theory, Vol. 45, No. 6, pp 2181-2191, September 1999    Non-Patent Document 2: G. Richter, M. Kaupper, and K. Sh. Zigangirov, “Irregular low-density parity-Check convolutional codes based on protographs,” Proceeding of IEEE ISIT 2006, pp 1633-1637    Non-Patent Document 3: J. Zhang, and M. P. C. Fossorier, “Shuffled iterative decoding,” IEEE Trans. Commun., vol. 53, no. 2, pp. 209-213, February 2005    Non-Patent Document 4: D. Hocevar, “A reduced complexity decoder architecture via layered decoding of LDPC codes,” in Signal Processing Systems SIPS 2004. IEEE Workshop on, pp. 107-112, October 2004    Non-Patent Document 5: B. Lu, G. Yue, and X. Wang, “Performance analysis and design optimization of LDPC-coded MIMO OFDM systems,” IEEE Trans. Signal Processing., vol. 52, no. 2, pp. 348-361, February 2004    Non-Patent Document 6: B. M. Hochwald, and S. ten Brink, “Achieving near-capacity on a multiple-antenna channel” IEEE Trans. Commun., vol. 51, no. 3, pp. 389-399, March 2003.    Non-Patent Document 7: S. Baro, J. Hagenauer, and M. Wizke, “Iterative detection of MIMO transmission using a list-sequential (LISS) detector” Proceeding of IEEE ICC 2003, pp 2653-2657.    Non-Patent Document 8: S. Lin, D. J. Jr., Costello, “Error control coding: Fundamentals and applications,” Prentice-Hall.    Non-Patent Document 9: R. D. Gallager, “Low-Density Parity-Check Codes,” Cambridge, Mass.: MIT Press, 1963.    Non-Patent Document 10: M. P. C. Fossorier, M. Mihaljevic, and H. Imai, “Reduced complexity iterative decoding of low density parity check codes based on belief propagation,” IEEE Trans. Commun., vol. 47, no. 5, pp. 673-680, May 1999.    Non-Patent Document 11: J. Chen, A. Dholakia, E. Eleftheriou, M. P. C. Fossorier, and X.-Yu Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun., vol. 53., no. 8, pp. 1288-1299, August 2005.